NSN | FSC | NIIN | CLS | Hazmat | DEMIL | Cancelled NSN |
---|---|---|---|---|---|---|
5962-00-481-8694 Item Description: MICROCIRCUIT,DIGITAL | 5962 | 004818694 | 0 | N | B | |
CIIC | HCC | ESD | PMIC | Criticality | ENAC | |
U | B | U | ||||
Part Number | ISC | RNVC | RNCC | HCC | MSDS | SADC |
477-0412-002 | 3 | 1 | 5 |
MRC | Criteria | Characteristic |
---|---|---|
ADAQ | BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES UM" |
ADAT | BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES UM" |
ADAU | BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES UM" |
AFGA | OPERATING TEMP RANGE | +0.0/+70.0 DEG CELSIUS" |
AFJQ | STORAGE TEMP RANGE | -55.0/+150.0 DEG CELSIUS" |
CBBL | FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND EDGE TRIGGERED AND POSITIVE OUTPUTS AND W/CLEAR AND W/ENABLE" |
CQSJ | INCLOSURE MATERIAL | PLASTIC" |
CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE" |
CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC" |
CQZP | INPUT CIRCUIT PATTERN | DUAL 4 INPUT" |
CSSL | DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE" |
CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL" |
TEST | TEST DATA DOCUMENT | 94756-477-0412 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRA" |
ADAQ | BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES UM" |
ADAT | BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES UM" |
ADAU | BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES UM" |
AFGA | OPERATING TEMP RANGE | +0.0/+70.0 DEG CELSIUS" |
AFJQ | STORAGE TEMP RANGE | -55.0/+150.0 DEG CELSIUS" |
CBBL | FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND EDGE TRIGGERED AND POSITIVE OUTPUTS AND W/CLEAR AND W/ENABLE" |
CQSJ | INCLOSURE MATERIAL | PLASTIC" |
CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE" |
CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC" |
CQZP | INPUT CIRCUIT PATTERN | DUAL 4 INPUT" |
CSSL | DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE" |
CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL" |
TEST | TEST DATA DOCUMENT | 94756-477-0412 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRA" |
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